Mobile communication devices generally transmit data in a bursty manner. In this regard, there are periods when there is no transmission and the device is quiet or inactive and others periods when there is a burst of communication followed again by a period of inactivity. These periods of bursts may occur during time slots or intervals when a mobile device may be authorized to access a communication channel. In order to effectively maximize use of channel bandwidth, while at the same time permit a plurality of access devices to share the bandwidth, very stringent timing requirements must be maintained. In some mobile communication devices, for example, timing requirements may be supplied and maintained by a voltage controlled crystal oscillator (VCXO). For example, in GSM, a voltage controlled crystal oscillator may be utilized to generate a very accurate 13 MHz clock. By fine-tuning a voltage of the VCXO, an output frequency of the VCXO may be more accurately controlled. This fine-tuning is often required in order to provide synchronization with the network.
FIG. 1 is a block diagram of an exemplary system that may be utilized to minimize the amount of power that is consumed. Referring to FIG. 1, there is shown an integrated circuit or chip 102 and an external voltage controlled crystal oscillator (VCXO) 106. The chip 102 may comprise a phase lock loop (PLL) 104, which is coupled to a plurality of on-chip devices D1, D2, D3 and D4. One of the on-chip devices, for example, D1, may be a main processor. Devices D2, D3 and D4 may be co-processors or accelerators. Devices D5 and D6 may be network interface modules and device D7 may be user interface modules, for example. The phase lock loop 104 may be utilized to generate a high frequency clock that is used to handle the demanding processing requirements during burst periods. The frequency of the phase lock loop 104 may be, for example, 156 MHz.
During normal operation, the VCXO 106 supplies a reference clock (C0) signal 110 to main PLL 104. The main PLL 104 then generates a plurality of output clocks that supplies clocking to on-chip devices D1, D2, D3, and D4. In this arrangement, a significant amount of power is consumed by the PLL 104 and on-chip devices D1, D2, D3 and D4. During standby mode when on-chip devices D1, D2, D3 and D4 are inactive, the main PLL 104 may be disabled and the reference clock 108 may be supplied to devices D5, D6 and D7. The reference clock 108 is derived from the VCXO 106 and is tapped off from the reference clock (C0) signal 110 that is supplied to the main PLL 104. Notwithstanding, even though the main PLL 104 is disabled, a significant amount of power is still drawn by the external voltage controlled crystal oscillator (VCXO) 106 during stand-by mode. This causes the batteries in mobile access devices to drain at a much faster rate. Accordingly, the batteries must be charged or changed more frequently.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.